Thursday, July 26, 2007

IC Design Flow

As seen in the figure, the IC Design Flow comprises of many steps. It starts with the detail design documentation, which acts as a basis for the behavioral description of the design. These behavioral description, coded in Verilog or VHDL, use constructs which are not necessarily synthesizable. This behavioral description is then simulated to see if the coded design works as intended. Errors, if any, can then be corrected in the behavioral description. The next step is to transform any non-synthesizable constructs into synthesizable one followed by the RTL simulation to confirm proper transformation of behavioral design into RTL.

This text description of design is required to be converted into actual hardware. This is achieved with the process called synthesis, which converts the high-level abstraction into gate-level netlist. Synthesis process takes RTL description, design constraints, design library as an input and generates the output netlist.

This gate-level netlist, along with timing information in the form of Standard Delay Format, sdf, file is then used to carry out the timing simulation. Errors, if any, would have to be corrected into RTL description and the process of synthesis is to be repeated again.

Once the design meets the timing requirements the next step is Placement and Routing. This determines the actual position of the design components on the chip and their interconnection details. This is an important steps and introduces the interconnection delays which are needed to be taken into consideration before the final fabrication step.

In the fabrication process, a mask is prepared for the design and is provided to foundry to produce the chips.

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